1. Field of the Invention
The present invention relates to a plating apparatus and a plating method, and more particularly to a plating apparatus and a plating method useful for forming interconnects by filling a conductive metal (interconnect material) such as copper (Cu) into fine interconnect patterns (recesses) formed in a substrate such as a semiconductor substrate.
2. Description of the Related Art
In recent years, instead of using aluminum or aluminum alloys as a material for forming interconnect circuits on a semiconductor substrate, there is an eminent movement towards using copper (Cu) that has a low electric resistivity and high electromigration resistance. Copper interconnects are generally formed by forming fine recesses for interconnects, such as trenches or via holes in a circuit form, in a semiconductor substrate, embedding the fine recesses with copper (interconnect material) by copper plating, and removing a copper layer (plated film) at portions other than the fine recesses by CMP or the like. In this damascene process, from the viewpoint of reducing loads on subsequent CMP, it is desirable that a copper plated film be deposited selectively in trenches or via holes in a circuit form, and that the amount of copper plated film deposited on portions other than the trenches or via holes be small. In order to achieve such an object, there have heretofore been proposed various ideas regarding a plating solution, such as composition in a bath of a plating solution or a brightener used in a plating solution.
Upon the electroplating for forming the copper layer, a copper sulfate plating solution containing copper sulfate and sulfuric acid in its composition is generally employed as a plating solution.
In recent years, more and more fine interconnects are formed in copper interconnects forming process for semiconductor devices, and design rules for such fine interconnects are considered to be changing from the 0.18 μm generation to the 0.13 μm generation and further to the 0.10 μm generation. Depending on circumstances, the advent of the seed-layer-less generation of semiconductor devices may not be impossible. With those more and more fine interconnects, unless the thickness of the seed layer is further reduced, the seed layer overhangs at the inlets of fine recesses, tending to produce voids in the plating process. In the 0.18 μm generation of design rules, the thickness of the seed layer is generally in the range from about 150 to 200 nm on the flat surface of the substrate. In the 0.13 μm generation of design rules, the thickness of the seed layer is about 50 nm in order to prevent voids from being produced in the plating process. In the 0.10 μm generation of design rules, the thickness of the seed layer will possibly be reduced to a range from about 5 to 25 nm.
A plating apparatus having the following configuration has been known as this type of plating apparatus used for plating to form fine interconnects having high aspect ratios. A substrate is held in such a state that a surface (surface to be plated) of the substrate faces upward (in a face-up manner). A cathode electrode is brought into contact with a peripheral portion of the substrate so that the surface of the substrate serves as a cathode. An anode is disposed above the substrate. While a space between the substrate and the anode is filled with a plating solution, a plating voltage is applied between the substrate (cathode) and the anode to plate a surface (surface to be plated) of a substrate (for example, see Japanese laid-open patent publication No. 2002-506489).
In a plating apparatus in which a substrate is held and plated in single wafer processing while a surface of the substrate faces upward, a distribution of a plating current can be made more uniform over an entire surface of the substrate to improve uniformity of a plated film over the surface of the substrate. Generally, the substrate is transferred and subjected to various processes in such a state that a surface of the substrate faces upward. Accordingly, it is not necessary to turn the substrate at the time of plating.
Meanwhile, in order to deposit a copper plated film selectively in trenches in a circuit form or the like, there has been known a method of bringing a porous member into contact with a substrate such as a semiconductor wafer, and plating the substrate while relatively moving the porous member in a contact direction (for example, see Japanese laid-open patent publication No. 2000-232078).
In order to detect the end point of plating and determine the timing of terminating plating in a plating apparatus of the type described above, there are generally employed a method in which plating is stopped when the plating time has reached a predetermined time, a method in which the quantity of electricity that has passed between a cathode and an anode is integrated, and plating is stopped when the integrated value has reached a predetermined value, and a method in which a thickness of a plated film is measured with a film-thickness monitor provided in the plating apparatus, and plating is stopped when the measured film thickness has reached a predetermined value.
For performing copper electroplating on the surface of a substrate, the outer circumferential portion of the substrate is come in contact with electrodes (electric contacts) to pass an electric current through the substrate. As the seed layer is thinner, the sheet resistance becomes higher immediately after the substrate starts to be plated, causing the plating current to concentrate on the outer circumferential portion of the substrate. The within-wafer thickness uniformity cannot be controlled only by a single shield plate for electric field correction.
The applicant has proposed a plating apparatus wherein a plating power source is connected individually to a plurality of split anodes to increase a current density at those split anodes positioned in a central area of the substrate to a level higher than at those split anodes positioned in a peripheral area of the substrate only during a certain period of time in which an initial plated film is formed on the substrate, thereby preventing the plating current from concentrating on the outer circumferential portion of the substrate, but allowing the plating current to flow to the central area of the substrate to make it possible to form a uniform plated film even if the sheet resistance is high (for example, see Japanese laid-open patent publication No. 2002-129383).